Preliminary Specifications: Programmed Data Processor Model Three (PDP-3): October, 1960

In Short

This technical specification details the design, hardware, and software environment of the PDP-3, a 36-bit parallel digital computer. It outlines a high-performance system built around a 5-microsecond magnetic core memory, solid-state transistor circuitry, and a flexible instruction set. Operating at speeds up to 200,000 operations per second, the architecture emphasizes structural restraint and economy. The document moves through central processing mechanics, standard and optional peripheral interfaces like magnetic tape and cathode ray displays, and the utility software required to assemble code and execute complex mathematics. It remains a classic artifact of early interactive computing design.

The Story

The manual unfolds by presenting the PDP-3 as a high-performance, large-scale general-purpose computer engineered for real-time control and central computing facilities. It immediately establishes the core philosophy of the machine: achieving reliability and low cost through transistorized static circuitry and deliberately excluding superfluous features. From this baseline, the architecture opens its technical framework, detailing a single-address system operating on 36-bit words, backed by a main coincident-current magnetic core memory consisting of 4096-word modules expandable to larger configurations.

The exposition advances into the central processing unit, laying out the register layout and data routing. Information flows through four primary 36-bit registers—including the Memory Buffer, Accumulator, and In-Out Register—and three 15-bit address registers. The text explains how the machine executes binary 1's complement arithmetic and handles address modification through multiple-step indirect addressing and 511 core memory registers functioning as automatic index registers. Instruction execution speeds range from 5 microseconds for single-cycle operations up to 90 microseconds for complex division.

Having established internal logic, the narrative transitions to physical operation and human interface mechanisms. The machine requires no special air-conditioned room preparation, running on standard AC power. The operator interacts through console toggle switches, such as Test Address, Test Word, and Sense Switches, alongside indicator lights and debugging aids like the Single Cycle Switch.

The text then shifts to peripheral communication. Standard input-output relies on a single transfer instruction operating through the In-Out Register to control a 300-line-per-second photoelectric paper tape reader, a paper tape punch, and an electric typewriter. Expansion capabilities are then detailed, presenting sophisticated subsystems: a 16-channel priority Sequence Break System for asynchronous interrupts, a High Speed In-Out Channel accessing memory directly, magnetic tape transports reading IBM formats, line printers, and interactive CRT displays complete with light pen peripherals.

The final phase addresses the software infrastructure essential to operate the hardware. It introduces the FRAP-3 assembly program for translating mnemonic symbols into machine code and the DECAL-3 compiler system with its recursive definition facilities. The manual concludes with a detailed accounting of floating-point subroutines, diagnostic maintenance routines used during voltage bias testing, and general utility programs that manage I/O communication, sealing a complete operational picture of the machine.

How It Unfolds

The architectural blueprint The design introduces a 36-bit solid-state computer operating at speeds up to 200,000 instructions per second. Built with static transistor flip-flops and 5-microsecond core memory, it eliminates complex extra hardware to maximize operating reliability.

The central processor and registers Data transfers take place across a structured layout of 36-bit data registers and 15-bit address registers. Memory indexing utilizes up to 511 internal core locations, while instructions process binary numbers using 1's complement arithmetic across one-cycle, two-cycle, and variable-step operations.

Physical controls and human intervention Console toggle switches and status indicators give operators direct access to internal machine states. Single-cycle and test switches allow engineers to step through memory operations for program debugging and system maintenance.

Input-output and peripheral interface Standard paper tape readers, tape punches, and electric typewriters handle basic data transfers through dedicated instruction codes. Optional high-speed channels, 16-channel interrupt systems, magnetic tape units, and CRT displays with light pens expand the machine into real-time environments.

Utility software and execution environment The system relies on the FRAP assembly program and DECAL compiler to translate user code into machine language. Floating-point subroutines handle advanced mathematics, while specialized maintenance routines monitor hardware stability under varying electrical loads.

The People

The Central Processor Functions as the main structural anchor of the machine, housing the Control Element, Arithmetic Element, and Memory Addressing Element. It aims to execute arithmetic logic and address bookkeeping at maximum speed without hardware overhead. It coordinates timing, governs instruction performance, and drives all data flow.

The Control Element Monitors instruction decoding and system timing through six-bit instruction registers and miscellaneous flip-flops. It seeks uninterrupted execution of instruction sequences, but yields control when encountering programmed wait states or hardware interrupt signals from external equipment.

The In-Out Register Acts as the central gateway for all peripheral communication and magnitude extension for multiplication and division. It strives to clear binary and alphanumeric data smoothly between external devices and internal storage, serving as the bridge for light pens, paper tape, and magnetic storage.

The Tape Control (TC) Manages information transfer between the computer and external magnetic tape drives. It seeks to format, read, and write 200-character-per-inch records while managing motion orders. It frequently encounters timing lags or parity errors, signaling program flags to resolve conflicts.

In Its Own Voice

"The simplicity of the system design excludes many marginal or superfluous features and thus their attendant cost and maintenance problems."

The opening description establishes the machine's core engineering philosophy of restraint.

"Shift or rotate instructions involving more than 33 steps can be used for simulating time delays."

The instruction section points out a practical programming trick hidden within standard register operations.

"An incidental fact which may be of importance in certain scientific or real time control applications is that the time origin of operations following an in-out completion pulse is identical with the time of that pulse."

The technical notes highlight the precise timing characteristics required for high-speed hardware integration.

What It's Really About

At its core, the text is about the functional elegance of minimal, modular computer design. It explores how a simple, well-chosen set of hardware primitives—such as single-address 36-bit words, flexible indirect addressing, and unified register structures—can handle complex real-time tasks without unnecessary hardware clutter. The manual argues that performance and operational reliability stem from restraint rather than overly complex feature sets. It examines the boundary between hardware and software, showing how complex tasks like floating-point mathematics or decimal conversion can be offloaded to tight subroutines while keeping the physical central processor fast, lean, and economically viable.

Why Read It Today

This specification offers a fascinating, unvarnished look at early computing history from the dawn of the transistor era. Modern programmers, computer historians, and hardware enthusiasts will enjoy tracing how fundamental architectural concepts—such as interrupt channels, index registers, memory-mapped I/O, and macro assembly—were conceptualized and explained in 1960.

Reading it feels like looking over the shoulder of a vintage systems engineer. The prose is clear, precise, and entirely devoid of corporate buzzwords. It treats the reader as a competent practitioner who simply needs to know memory cycle times, register bit assignments, and instruction execution delays. The primary difficulty lies in its dense, highly technical nature: the text consists of machine code mnemonics, bit-layout specifications, octal address tables, and timing formulas like $5 + 0.2N\text{ microseconds}$. Yet for those interested in the mechanics of early mainframe computing, it stands as an authentic, remarkably crisp portrait of early DEC engineering design.